A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance AnalysisReport as inadecuate




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Presented at: IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (VLSI-SoC), Perth, Australia, October 17-19 Published in: Proceedings of the IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (VLSI-SoC), p. 199-204 IFIP, 2005

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for a-priori functional fault tolerance analysis was developed. It is a statistical Monte Carlo based tool that induces different failure models, and does subsequent evaluation of system reliability under realistic constraints. A structured fault modeling architecture is also proposed, which is together with the tool a part of the new design method representing a compatible improvement of existing IC design methodologies.

Keywords: reliability ; nanometar-scale design ; fault modeling ; design methodologies ; a-priori estimation ; Monte Carlo analysis Reference LSM-CONF-2005-007





Author: Stanisavljevic, Milos; Abhishek, Vineet; Schmid, Alexandre; Leblebici, Yusuf

Source: https://infoscience.epfl.ch/record/55862?ln=en







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