NoC emulation: a tool and design flow for MPSoCReport as inadecuate




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Published in: Circuits and Systems Magazine, IEEE, vol. 7, num. 4, p. 42 - 51 Publication date: 2007

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing; thus, the amount of processors, memories and application-specific signal pro- cessing cores is rapidly increasing. In these new Multi- Processor SoCs, (MPSoCs) one of the most critical elements regarding overall efficiency is on-chip interconnections. Network-On-Chip(NoC) provides a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or ad hoc topologies and can be tuned by a large set of parameters. Simulation and functional validation are essential to assess the correctness and performance of MPSoC architectures. We present a flexible hardware-software emulation framework implemented on an FPGA that is specially designed to suitably explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy and flexibility of software simulators. Finally, we propose a validation flow for MPSoCs based on our flexible NoC emulation framework, which allows designers to explore and optimize a range of solutions, as well as quickly characterize performance figures and identify possible limitations in their on-chip interconnection architectures.

Reference EPFL-ARTICLE-117032doi:10.1109/MCAS.2007.910029View record in Web of Science





Author: Genko, Nicolas; Atienza, David; De Micheli, Giovanni; Benini, Luca

Source: https://infoscience.epfl.ch/record/117032?ln=en







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