An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar CodesReport as inadecuate




An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes - Download this document for free, or read online. Document in PDF available to download.

Presented at: 2015 IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt, December 6-9, 2015 Publication date: 2015

Reference EPFL-CONF-214753





Author: Wüthrich, Johannes Martin; Balatsoukas Stimming, Alexios Konstantinos; Burg, Andreas Peter

Source: https://infoscience.epfl.ch/record/214753?ln=en



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