Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power ConsumptionReport as inadecuate

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Lausanne: EPFL, 2016

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. With all these innovations and efforts, the transistor size is approaching the natural limitations of materials in the near future. The circuits are expected to compute in a more efficient way. From this perspective, new device concepts are desirable to exploit additional functionality. On the other hand, with the continuously increased device density on the chips, reducing the power consumption has become a key concern in IC design. To overcome the limitations of Complementary Metal-Oxide-Semiconductor (CMOS) technology in computing efficiency and power reduction, this thesis introduces the multiple- independent-gate Field-Effect Transistors (FETs) with silicon nanowires and FinFET structures. The device not only has the capability of polarity control, but also provides dual-threshold- voltage and steep-subthreshold-slope operations for power reduction in circuit design. By independently modulating the Schottky junctions between metallic source/drain and semiconductor channel, the dual-threshold-voltage characteristics with controllable polarity are achieved in a single device. This property is demonstrated in both experiments and simulations. Thanks to the compact implementation of logic functions, circuit-level benchmarking shows promising performance with a configurable dual-threshold-voltage physical design, which is suitable for low-power applications. This thesis also experimentally demonstrates the steep-subthreshold-slope operation in the multiple-independent-gate FETs. Based on a positive feedback induced by weak impact ionization, the measured characteristics of the device achieve a steep subthreshold slope of 6 mV/dec over 5 decades of current. High Ion/Ioff ratio and low leakage current are also simultaneously obtained with a good reliability. Based on a physical analysis of the device operation, feasible improvements are suggested to further enhance the performance. A physics-based surface potential and drain current model is also derived for the polarity-controllable Silicon Nanowire FETs (SiNWFETs). By solving the carrier transport at Schottky junctions and in the channel, the core model captures the operation with independent gate control. It can serve as the core framework for developing a complete compact model by integrating advanced physical effects. To summarize, multiple-independent-gate SiNWFETs and FinFETs are extensively studied in terms of fabrication, modeling, and simulation. The proposed device concept expands the family of polarity-controllable FETs. In addition to the enhanced logic functionality, the polarity-controllable SiNWFETs and FinFETs with the dual-threshold-voltage and steep-subthreshold-slope operation can be promising candidates for future IC design towards low-power applications.

Keywords: nanowire ; FinFET ; steep-subthreshold-slope ; multi-threshold-voltage ; polarity control ; simulation ; compact modeling ; fabrication ; logic design ; low power Thèse École polytechnique fédérale de Lausanne EPFL, n° 6884 (2016)Programme doctoral Microsystèmes et MicroélectroniqueFaculté informatique et communicationsInstitut des systèmes informatiques et multimédiasLaboratoire des systèmes intégrés (IC/STI)Jury: Prof. Yusuf Leblebici (président) ; Prof. Giovanni De Micheli (directeur de thèse) ; Prof. Elison Matioli, Dr Walter Michael Weber, Dr Maud Vinet (rapporteurs) Public defense: 2016-1-11 Reference doi:10.5075/epfl-thesis-6884Print copy in library catalog

Author: Zhang, JianAdvisor: De Micheli, Giovanni


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