Error Immune Logic for Low-Power Probabilistic ComputingReport as inadecuate

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VLSI DesignVolume 2010 2010, Article ID 460312, 9 pages

Research ArticleSchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA

Received 27 May 2009; Accepted 19 November 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 Bo Marr et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronousdesign for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 𝜇m technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

Author: Bo Marr, Jason George, Brian Degnan, David V. Anderson, and Paul Hasler



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