Theory, Analysis and Implementation of an On-Line BIST TechniqueReport as inadecuate

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VLSI Design - Volume 1 1993, Issue 1, Pages 9-22

Cadence Design Systems Inc., Lowell, Massachusetts, USA

Department of Electrical and Computer Engineering, University of Wisconsin, Madison, Wisconsin, USA

Copyright © 1993 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A Built-ln Concurrent Self-Test BICST technique for testing combinational logic circuits concurrently with theirnormal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce theoverall area overhead is introduced. The method was implemented in the design of an ALU with on-line testcapability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip areaand it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increasein the size of the ALU.

Following the description of the BICST technique, measures for evaluating the performance of the BICSTtechnique are defined. Methods for the computation of the performance measures using analytical and simulationtechniques are discussed and results of these methods are reported. Methods for detecting intermittent faults andfor computing the transient fault coverage using BICST are also described. The impact of BICST on the systemdiagnostics and system maintenance is discussed.

Author: Rajiv Sharma and Kewal K. Saluja



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