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Abstract: One of the main bottlenecks when designing a network processing system isvery often its memory subsystem. This is mainly due to the state-of-the-artnetwork links operating at very high speeds and to the fact that in order tosupport advanced Quality of Service QoS, a large number of independent queuesis desirable. In this paper we analyze the performance bottlenecks of variousdata memory managers integrated in typical Network Processing Units NPUs. Weexpose the performance limitations of software implementations utilizing theRISC processing cores typically found in most NPU architectures and we identifythe requirements for hardware assisted memory management in order to achievewire-speed operation at gigabit per second rates. Furthermore, we describe thearchitecture and performance of a hardware memory manager that fulfills thoserequirements. This memory manager, although it is implemented in areconfigurable technology, it can provide up to 6.2Gbps of aggregatethroughput, while handling 32K independent queues.



Author: I. Papaefstathiou, T. Orphanoudakis, G. Kornaros, C. Kachris, I. Mavroidis, A. Nikologiannis

Source: https://arxiv.org/







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