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Abstract: On-chip networks have been proposed as the interconnect fabric for futuresystems-on-chip and multi-processors on chip. Power is one of the mainconstraints of these systems and interconnect consumes a significant portion ofthe power budget. In this paper, we propose four leakage-aware interconnectschemes. Our schemes achieve 10.13%~63.57% active leakage savings and12.35%~95.96% standby leakage savings across schemes while the delay penaltyranges from 0% to 4.69%.



Author: Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin

Source: https://arxiv.org/







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