At-Speed Logic BIST for IP Cores - Computer Science > Hardware ArchitectureReport as inadecuate




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Abstract: This paper describes a flexible logic BIST scheme that features high faultcoverage achieved by fault-simulation guided test point insertion, realat-speed test capability for multi-clock designs without clock frequencymanipulation, and easy physical implementation due to the use of a low-speed SEsignal. Application results of this scheme to two widely used IP cores are alsoreported.



Author: B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, S. Wu

Source: https://arxiv.org/



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