Charge Pump Circuits for Low-voltage ApplicationsReport as inadecuate

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VLSI Design - Volume 15 2002, Issue 1, Pages 477-483

Department of Informatics, Division of Communications and Signal Processing, University of Athens, Panepistimiopolis, Athens 157 84, Greece

Institute of Microelectronics, NCSR “Demokritos”, Aghia Paraskevi 153 10, Greece

HELIC S.A., 75 Poseidonos av., Athens 174 55, Greece

Received 1 February 2001; Revised 26 March 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications 1.2 V, 0.9 V, where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers charge pump with CVD are also proposed. The first utilises PMOS transistors charge pump with CVD-PMOS in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude charge pump with CVD-BCLK. Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.

Author: Y. Moisiadis, I. Bouras, and A. Arapoyanni



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