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VLSI Design - Volume 7 1998, Issue 3, Pages 289-301

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA



Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We propose a logic synthesis system that includes power optimization after technologymapping. Our approach is unique in that our post-mapping logic transformations takeinto account information on circuit delay, capacitance, arrival times, glitches, etc., toprovide much better accuracy than previously proposed technology-independent poweroptimization methods. By changing connections in a mapped circuit, we achieve powerimprovements up to 13% in case of area- or delay-optimized circuits, with reductionsalso in area and delay. We show that by applying the proposed technique on circuitsthat are already restructured for lower switching activity using the technique presentedin 11, total power savings up to 59% in case of area-optimized circuits and 38% in caseof delay-optimized circuits are achievable. The post-mapping transformations are basedon the transition density model of circuit switching activity and the concept ofpermissible logic functions. The techniques presented here are applicable equally well toboth synchronous and asynchronous circuits. The power measurements are done undera general delay model.





Author: Rajendran Panda and Farid N. Najm

Source: https://www.hindawi.com/



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