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Dither-less digital PLL, Mixed mode phase accumulator, Hybrid phase detector

Nag, Amlan

Supervisor and department: Hossain, Masum Electrical and Computer Engineering

Examining committee member and department: Elliot Duncan Electrical and Computer Engineering Moez, Kambiz Electrical and Computer Engineering Hossain, Masum Electrical and Computer Engineering

Department: Department of Electrical and Computer Engineering

Specialization: Integrated Circuits and Systems

Date accepted: 2016-08-12T10:17:33Z

Graduation date: 2016-06:Fall 2016

Degree: Master of Science

Degree level: Master's

Abstract: Low phase noise frequency synthesizers are of primary importance in modern RF communication systems to maintain signal integrity. Since current technologies are going mobile, without much reduction of operating speed, a low phase noise TDC less digital PLL is proposed in this thesis. A dual edge sampled hybrid PD is proposed and incorporated in the PLL design. It consists of an analog S-H circuit and a hard decision circuit. The decision circuit serves as a Bang Bang PD BBPD, while analog sampled voltage provides continuous phase error information. Mixed mode phase accumulator, which is a combination of a continuous time phase accumulator VCO and a discrete time phase accumulator DTPA, is used which gives direct control over oscillator phase, without actually changing the phase-frequency of VCO. Quantization noise introduced by the BBPD is not eliminated, but bypassed in the feedback path with the help of hybrid PD and mixed mode phase accumulator without altering VCO control nodes. Therefore, this PLL generates a clean ditherless clock signal almost comparable to analog PLL. The design implementation, circuit simulation and measurement results of the proposed dither-less DPLL is presented in this dissertation. The prototype chip fabricated in 65nm CMOS process occupies a die area of 0.15275 mm2 and achieves a phase noise of -123 dBc-Hz at 1 MHz offset with 264 fs integrated jitter.

Language: English

DOI: doi:10.7939-R31N7XV74

Rights: This thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for the purpose of private, scholarly or scientific research. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.





Author: Nag, Amlan

Source: https://era.library.ualberta.ca/


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A Low Jitter Digital PLL based on Mixed Mode Phase Accumulator by Amlan Nag A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science [in Integrated Circuits and Systems] Department of Electrical & Computer Engineering University of Alberta © Amlan Nag, 2016 Abstract Low phase noise frequency synthesizers are of primary importance in modern RF communication systems to maintain signal integrity.
Since current technologies are going mobile, without much reduction of operating speed, a low phase noise TDC less digital PLL is proposed in this thesis.
A dual edge sampled hybrid PD is proposed and incorporated in the PLL design.
It consists of an analog S-H circuit and a hard decision circuit.
The decision circuit serves as a Bang Bang PD (BBPD), while analog sampled voltage provides continuous phase error information.
Mixed mode phase accumulator, which is a combination of a continuous time phase accumulator (VCO) and a discrete time phase accumulator (DTPA), is used which gives direct control over oscillator phase, without actually changing the phase-frequency of VCO.
Quantization noise introduced by the BBPD is not eliminated, but bypassed in the feedback path with the help of hybrid PD and mixed mode phase accumulator without altering VCO control nodes.
Therefore, this PLL generates a clean ditherless clock signal almost comparable to analog PLL. The design implementation, circuit simulation and measurement results of the proposed ditherless DPLL is presented in this dissertation.
The prototype chip fabricated in 65nm CMOS process occupies a die area of 0.15275 mm2 and achieves a phase noise of -123 dBc-Hz at 1 MHz offset with 264 fs integrated jitter. II Acknowledgements I have received a lot of tangible and intangible help from various sources, institutions and academicians to complete my research work.
At the fist juncture I would like to place my indebtedness and utmost gratitude to my supervisor, Prof.
Masum Hussain...





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