Design and implementation of a content aware image processing module on FPGAReport as inadecuate


Design and implementation of a content aware image processing module on FPGA


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In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design a low power content aware system that is able to take an image from an image sensor, determine blocks in the image that contain important information and encode those block for transmission thus reducing the overall transmission effort. At the same time, the encoder and the preprocessor must not consume so much computation power that the utility of this system is lost.We have implemented such a system which uses a combination of Edge Detection and Frame Differencing to determine useful information within an image. A JPEG encoder then encodes the important blocks for transmission. An implementation on a FPGA is presented in this work. This work demonstrates that preprocessing gives us a 48.6 % reduction in power for a single frame while maintaining a delivery ratio of above 85 % for the given set of test frames.



Georgia Tech Theses and Dissertations - School of Electrical and Computer Engineering Theses and Dissertations -



Author: Mudassar, Burhan Ahmad - -

Source: https://smartech.gatech.edu/







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