Error Correction Circuit for Single-Event Hardening of Delay Locked LoopsReport as inadecuate




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In scaled CMOS processes,the single-event effects generate missing output pulses in Delay-Locked LoopDLL. Due to its effective sequence detection of the missing pulses in theproposed Error Correction Circuit ECC and its portability to be applied toany DLL type, the ECC mitigates the impact of single-event effects andcompletes its operation with less design complexity without any concern about losingthe information. The ECC has been implemented in 180 nm CMOS process andmeasured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2-mg.The robustness and portability of the mitigation technique are validatedthrough the results obtained by implementing proposed ECC in XilinxArtix 7FPGA.

KEYWORDS

Delay-Locked Loop, Single Event Transients, Error Correction Circuit

Cite this paper

Balaji, S. and Ramasamy, S. 2016 Error Correction Circuit for Single-Event Hardening of Delay Locked Loops. Circuits and Systems, 7, 2437-2442. doi: 10.4236-cs.2016.79210.





Author: S. Balaji1, S. Ramasamy2

Source: http://www.scirp.org/



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