High-Performance RMA-Based Broadcast on the Intel SCCReport as inadecuate




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1 EPFL - Ecole Polytechnique Fédérale de Lausanne

Abstract : Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel Single-Chip Cloud Computer SCC is a prototype of a message-passing many-core chip. It offers the ability to move data between on-chip Message Passing Buffers MPB using Remote Memory Access RMA. Performance of message-passing applications is directly affected by efficiency of collective operations, such as broadcast. In this paper, we study how to make use of the MPBs to implement an efficient broadcast algorithm for the SCC. We propose OC-Bcast On-Chip Broadcast, a pipelined k-ary tree algorithm tailored to exploit the parallelism provided by on-chip RMA. Using a LogP-based model, we present an analytical evaluation that compares our algorithm to the state-of-the-art broadcast algorithms implemented for the SCC. As predicted by the model, experimental results show that OC-Bcast attains almost three times better through-put, and improves latency by at least 27%. Furthermore, the analytical evaluation highlights the benefits of our approach: OC-Bcast takes direct advantage of RMA, unlike the other considered broadcast algorithms, which are based on a higher-level send-receive interface. This leads us to the conclusion that RMA-based collective operations are needed to take full advantage of hardware features of future message-passing many-core architectures.

Keywords : RMA HPC Many-Core Chips Message Passing Broadcast





Author: Darko Petrović - Omid Shahmirzadi - Thomas Ropars - André Schiper -

Source: https://hal.archives-ouvertes.fr/



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