Mitigating Time Interval Error TIE in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-LinesReport as inadecuate




Mitigating Time Interval Error TIE in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines - Download this document for free, or read online. Document in PDF available to download.

A major concern inmodern smart-phones and hand-held devices is a way of mitigating the timeinterval error TIE perceived at high-speed digital transits along the tracesof the circuit-board rigid and or flexible used in baseband infrastructures.Indicated here is a way of adopting a planar fractal inductor configuration toimprovise the necessary time-delay in the transits of digital signal phasejitter and reduce the TIE. This paper addresses systematic designconsiderations on fractal inductor geometry commensurate with practical aspectsof its implementation as delaylines in the high-speed digital transports atthe baseband operations of smart-phone infrastructures. Experimental resultsobtained from a test module are presented to illustrate the efficacy of the design and acceptable delayperformance of the test structure commensurate with the digital transports ofinterest.

KEYWORDS

Time-Interval Error, Smart-Phones, Fractal Inductors, Delay-Lines Insert

Cite this paper

Neelakanta, P. and Noori, A. 2014 Mitigating Time Interval Error TIE in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines. Circuits and Systems, 5, 115-123. doi: 10.4236-cs.2014.55013.





Author: Perambur S. Neelakanta, Aziz U. Noori

Source: http://www.scirp.org/



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