Implementation of a Synchronized Oscillator Circuit for Fast Sensing and Labeling of Image ObjectsReport as inadecuate




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1

Institute of Electronics, Technical University of Lodz, Wolczanska 211-215, 90-924 Lodz, Poland

2

Division of Electronics and Information Engineering, Chonbuk National University, 561-756 Jeonju, Korea





*

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Abstract We present an application-specific integrated circuit ASIC CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a -temporary correlation- theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person’s attention if he or she is focused on a coherent stimulus image object. For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 mm C035M-D 5M-1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented. View Full-Text

Keywords: synchronized oscillator network; parallel image segmentation; labeling; VLSI CMOS implementation synchronized oscillator network; parallel image segmentation; labeling; VLSI CMOS implementation





Author: Jacek Kowalski 1, Michal Strzelecki 1,* and Hyongsuk Kim 2

Source: http://mdpi.com/



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