A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAsReport as inadecuate




A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs - Download this document for free, or read online. Document in PDF available to download.

EURASIP Journal on Advances in Signal Processing

, 2003:804527

1.Department of Electrical and Computer EngineeringUniversity of CalgaryCalgaryCanada

Cite this article as: Carreira, A., Fox, T.W. & Turner, L.E. EURASIP J. Adv. Signal Process. 2003 2003: 804527. https:-doi.org-10.1155-S1110865703301015 DOI https:-doi.org-10.1155-S1110865703301015 Publisher Name Springer International Publishing Online ISSN 1687-6180 About this journal Personalised recommendations

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Author: Alex Carreira1

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