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1 IMS - Laboratoire de l-intégration, du matériau au système 2 LESTER - Laboratoire d-Electronique des Systèmes TEmps Réel 3 Lab-STICC UBS CACS MOCS Lab-STICC - Laboratoire des sciences et techniques de l-information, de la communication et de la connaissance

Abstract : The increasing needs of higher data rates associated with mobility constraints motivate the development of Digital Satellite News Gathering DSNG and Digital Video Broadcasting applications by Satellite DVB S. Error control codes like Reed-Solomon and Viterbi codes are widely used in these communication systems against channel noise. Traditional methods for rapid prototyping of hardware cores for this kind of applications are based on RTL specifications However, they suffer from heavy limitations that prevent them from efficiently addressing both the algorithmic complexity and the high flexibility required by the various application profiles in fast implementation and prototyping issues. For this reasons, we propose to reduce hardware IP core development time by benefiting from the emerging High-Level Synthesis HLS tools in a platform-based approach dedicated to rapid prototyping. This technique has been successfully applied to the design of Reed-Solomon RS and Viterbi decoder IP cores for the DVB-DSNG standard and can be easily extended to many DSP dataflow applications.

Keywords : High level synthesis Reed Salomon DSP application





Author: Bertrand Le Gal - Emmanuel Casseau - Pierre Bomel - Chirstophe Jégo - Nathalie Le Héno - Eric Martin -

Source: https://hal.archives-ouvertes.fr/



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