A new Low-Power recoding algorithm for multiplierless single-multiple constant multiplication.Report as inadecuate




A new Low-Power recoding algorithm for multiplierless single-multiple constant multiplication. - Download this document for free, or read online. Document in PDF available to download.

1 CTDA - Centre de Développement des Technologies Avancées 2 FEMTO-ST - Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies

Abstract : Optimizing the number of additions in constant coefficient multiplication is conjectured to be a NP-hard problem. In this paper, we report a new heuristic requiring an average of 29.10 % and 10.61 % less additions than the standard canonical signed digit representation CSD and the double base number system DBNS, respectively, for 64-bit coefficients. The maximum number of additions per coefficient is bounded by N-4+2, and the time-complexity of the recoding is linearly proportional to N, where N is the bit-size of the constant. These performances are achieved using a new redundant version of radix-28 recoding.





Author: Abdelkrim K. Oudjida - Mohamed L. Berrandjia - Nicolas Chaillet -

Source: https://hal.archives-ouvertes.fr/



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