Development of an On-Chip Sensor for Substrate Coupling Study in Smart Power Mixed ICsReport as inadecuate

Development of an On-Chip Sensor for Substrate Coupling Study in Smart Power Mixed ICs - Download this document for free, or read online. Document in PDF available to download.

* Corresponding author 1 LAAS-ESE - Équipe Énergie et Systèmes Embarqués LAAS - Laboratoire d-analyse et d-architecture des systèmes Toulouse

Abstract : In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits ICs are extensively used. Electrical noise induced by power stage switching or external disturbances generates parasitic substrate currents, leading to a local shift of the substrate potential which can severely disturb low voltage circuits. Nowadays this is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an on-chip noise sensor dedicated to measurements of transient voltage fluctuations induced by high voltage activity and coupled by the substrate. Index Terms— on-chip sensor; Smart Power IC; substrate noise coupling; electromagnetic compatibility; substrate parasitic bipolar structures; I. INTRODUCTION Nowadays, many segments of microelectronics move towards monolithic system integration merging on the same IC Smart power ICs low voltage analog and-or digital parts with high voltage parts using power transistors. Substrate coupling in Smart power ICs occurs when parasitic bipolar structures with unpredictable size and location are activated after an injection of current into the substrate due to internal switching activity or external noise coupling. When low power analog and digital applications are integrated with high voltage HV devices on the same IC, these side effects become very important and hurtful to the circuit operation. In turn, designers have to rely on empirical basis for the design strategy, which is expensive and time consuming. Today, when simulating circuits with HV-MOSFETS devices, their specific SPICE models are used in every CAD tool but these models do not address generation of these parasitic substrate currents of minority and majority carriers. AUTOMICS project 1 aims at providing SPICE models, once implemented in CAD tools, will allow optimizing high voltage and high current capability, EMI-EMC performance with respect to substrate parasitic robustness.

Author: Veljko Tomasevic - Alexandre Boyer - Sonia Ben Dhia -



Related documents