Timing Issues of Transient Faults in Concurrent Error Detection SchemesReport as inadecuate

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* Corresponding author 1 SysMIC - Conception et Test de Systèmes MICroélectroniques LIRMM - Laboratoire d-Informatique de Robotique et de Microélectronique de Montpellier

Abstract : This work reveals additional timing difficulties by which concurrent error detection CED schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in combinational logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed whether flip-flops are used to register the error signals, and so timing conditions are suggested for a more efficient use of them.

Keywords : and security fault tolerance soft errors fault attacks concurrent error dectection codes transient faults

Author: Rodrigo Possamai Bastos - Giorgio Di Natale - Marie-Lise Flottes - Bruno Rouzeyre -

Source: https://hal.archives-ouvertes.fr/


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