Zero-defect designs, why and how: formal verification vs. automated synthesisReport as inadecuate




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1 TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture 2 Polito - Politecnico di Torino Torino

Abstract : Zero-defect VLSI design is a goal one must try to reach and CAD tools provide an increasingly important support to designers. High-level automated synthesis and formal verification are cooperating approaches to this end. The paper analyzes the general framework of digital design and the relationships between synthesis and verification as far as functional correctness is concerned, showing their limits, mutual dependencies, and how they can and should work together.

Keywords : zero-defect-VLSI-design equivalence-preserving-transformations formal-verification automated-synthesis functional-correctness digital-design CAD-tools





Author: D. Borrione - P. Prinetto -

Source: https://hal.archives-ouvertes.fr/



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