Enabling the UCD-SPH code on the Xeon PhiReport as inadecuate




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* Corresponding author 1 ICHEC - Irish Centre for High-End Computing 2 Carnegie Wave Energy Ltd 3 School of Mathematical Sciences 4 LAMA - Laboratoire de Mathématiques 5 ICHEC - Irish Centre for High-End Computing

Abstract : This white-paper reports on our efforts to enable an SPH-based Fortran code on the Intel Xeon Phi. As a result of the work described here , the two most computationally intensive subroutines rates and shepard beta of the UCD-SPH code were refactored and parallelised with OpenMP for the first time, enabling the code to be executed on multi-core and many-core shared memory systems. This parallelisation achieved speedups of up to 4.3x for the rates subroutine and 6.0x for the shepard beta subroutine resulting in overall speedups of up to 4.2x on a 2 processor Sandy Bridge Xeon E5 machine. The code was subsequently enabled and refactored to execute in different modes on the Intel Xeon Phi co-processor achieving speedups of up to 2.8x for the rates subroutine and up to 3.8x for the shepard beta subroutine producing overall speedups of up to 2.7x compared to the original unoptimised code. To explore the capabilities of auto-vectorisation the shepard beta subroutine was refactored which results in speedups of up to 6.4x for the shepard beta subroutine relative to the original unoptimised version of the shepard beta subroutine. The development and testing phases of the project were carried out on the PRACE EURORA machine.





Author: Christian Lalanne - Ashkan Rafiee - Denys Dutykh - Michael Lysaght - Frédéric Dias -

Source: https://hal.archives-ouvertes.fr/



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