FPGA-based many-core System-on-Chip designReport as inadecuate




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1 CES Lab - Computer & Embedded Systems 2 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages Inria Lille - Nord Europe, CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189

Abstract : Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data SIMD many-core architec-tures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property IP cores and FPGAs Field Pro-grammable Gate Arrays, on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architectures





Author: Mouna Baklouti - Philippe Marquet - Jean-Luc Dekeyser - Mohamed Abid -

Source: https://hal.archives-ouvertes.fr/



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