G-MPSoC: Generic Massively Parallel Architecture on FPGAReport as inadecuate

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1 Inria Lille - Nord Europe 2 CES Lab - Computer & Embedded Systems 3 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages Inria Lille - Nord Europe, CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189

Abstract : Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms filtering, correlation, etc. and their numerous parameters. Having a flexible and pro-grammable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we propose in this paper Generic Massively Parallel architecture G-MPSoC. G-MPSoC is a System-on-Chip based on a grid of clusters of Hardware and Software Computation Elements with different size, performance, and complexity. It is composed of parametric IP-reused modules: processor, controller, accelerator, memory, interconnection network, etc. to build different architecture configurations. The generic structure of G-MPSoC facilitates its adaptation to the intensive signal processing applications requirements. This paper presents G-MPSoC architecture and details its different components. The FPGA-based implementation and the experimental results validate the architectural model choice and show the effectiveness of this design.

Keywords : IP-reused parallelism Key–Words: SoC FPGA MPP Generic architecture

Author: Hana Krichene - Mouna Baklouti - Mohamed Abid - Philippe Marquet - Jean-Luc Dekeyser -

Source: https://hal.archives-ouvertes.fr/


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