3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron TechnologyReport as inadecuate




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1 GIPSA-AGPIG - AGPIG GIPSA-DIS - Département Images et Signal 2 ENSTA ParisTech UEI - Unité d-Électronique et d-informatique

Abstract : In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.





Author: Dominique Houzet - Mohammad Jabbar - Omar Hammami -

Source: https://hal.archives-ouvertes.fr/



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