Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETsReport as inadecuate




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1 INL - Institut des nanotechnologies de Lyon - Site d-Ecully

Abstract : This work presents a new style of gate-level reconfigurable cells based on the double-gate DG MOSFET device. The proposed dynamic- and static-logic cells demonstrate significant gate area reductions compared to conventional CMOS lookup table LUT techniques between 80-95% while configuration memory requirements are also reduced up to 60%. Simulation results show that it can be used either in low power reconfigurable applications up to 90% power reduction is possible or for speeds comparable to those of CMOS-LUTs.





Author: Ian O-Connor - Ilham Hassoune - David Navarro -

Source: https://hal.archives-ouvertes.fr/



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