AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUEReport as inadecuate




AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE - Download this document for free, or read online. Document in PDF available to download.

1 L@BISEN - Laboratoire ISEN-Brest

Abstract : In this paper we present a novel architecture for FFT implementation on FPGA. The proposed architecture based on radix-4 algorithm presents the advantage of a higher throughput and low area-delay product. In fact, the novelty consists on using a memory sharing and dividing technique along with parallel-in parallel-out Processing Elements PE. The proposed architecture can perform N-point FFT using only 4-3N delay ele- ments and involves a latency of N-4 cycles. Comparison in terms of hardware complexity and area-delay product with recent works presented in the literature and commercial IPs has been made to show the efficiency of the proposed design. Moreover, from the experimental results obtained from a FPGA prototype we find that the proposed design involves an execution time of 56% lower than that obtained with Xilinx IP core and an increase of 19% in the throughput by area ratio for 256-point FFT.

keyword : Digital hardware implementation VLSI embedded signal processing





Author: Yousri Ouerhani - Maher Jridi - Ayman Alfalou -

Source: https://hal.archives-ouvertes.fr/



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