Effects of I-O Routing through Column Interfaces in Embedded FPGA FabricsReport as inadecuate




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1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE 2 ECE - Department of Electrical and Computer Engineering - University of Massachusetts

Abstract : The emergence of 2.5D and 3D packaging technologies enables the integration of FPGA dice into more complex systems. Both heterogeneous manycore designs, which include an FPGA layer, and interposer-based multi-FPGA systems support the inclusion of reconfigurable hardware in 3D-stacked integrated circuits. In these architectures, the communication between FPGA dice or between FPGA and fixed-function layers often takes place through dedicated communication interfaces spread over the FPGA logic fabric, as opposed to an I-O ring around the fabric. In this paper, we investigate the effect of organizing FPGA fabric I-O into coarse-grained interface blocks distributed throughout the FPGA fabric. Specifically, we consider the quality of results for the placement and routing phases of the FPGA physical design flow. We evaluate the routing of I-O signals of large applications through dedicated interface blocks at various granularities in the logic fabric, and study its implications on the critical path delay of routed designs. We show that the impact of such I-O routing is limited and can improve chip routability and circuit delay in many cases.

Keywords : FPGA 3D ICs 2.5D ICs Dedicated I-O routing





Author: Christophe Huriaux - Olivier Sentieys - Russell Tessier -

Source: https://hal.archives-ouvertes.fr/



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