A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array ArchitectureReport as inadecuate

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VLSI Design - Volume 4 1996, Issue 2, Pages 119-133

Electrical Engineering Dept., Yonsei University, Seoul, Korea

Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin 78712, TX, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element PE array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.

This new approach provides for a high performance, cost effective, gain over software simulation. Simulation results show that the hardware accelerator is orders of magnitude faster than the software simulation program.

Author: Sungho Kang, Youngmin Hur, and Stephen A. Szygenda

Source: https://www.hindawi.com/


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