Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack ResistanceReport as inadecuate




Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance - Download this document for free, or read online. Document in PDF available to download.

Journal of Electrical and Computer Engineering - Volume 2014 2014, Article ID 837572, 13 pages -

Research Article

Samsung Electronics, Austin, TX 78754, USA

Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA

Department of Electrical and Computer Engineering, Missouri University of Science & Technology, Rolla, MO 65409, USA

Received 18 February 2014; Revised 22 May 2014; Accepted 22 May 2014; Published 20 July 2014

Academic Editor: Sos Agaian

Copyright © 2014 Siva Kotipalli et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES advanced encryption standard Key Expander and Round Function, which offer increased side-channel attackSCA resistance. These designs are based on a delay-insensitive DI logic paradigm known as null convention logic NCL, which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise SNR ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO weighted average simultaneous switching output analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.





Author: Siva Kotipalli, Yong-Bin Kim, and Minsu Choi

Source: https://www.hindawi.com/



DOWNLOAD PDF




Related documents