A Split Island Layout Style of Butting-Inserted Substrate Pickups for NMOSFET ESD ReliabilityReport as inadecuate




A Split Island Layout Style of Butting-Inserted Substrate Pickups for NMOSFET ESD Reliability - Download this document for free, or read online. Document in PDF available to download.

Advances in Materials Science and Engineering - Volume 2015 2015, Article ID 691403, 9 pages -

Research Article

Department of Electronics Engineering, Chien Hsin University of Science and Technology, No. 229, Chien-Hsin Road, Zhongli District, Taoyuan City 320, Taiwan

Department of Electronic Engineering, Ming Chuan University, No. 5 De Ming Road, Gui-Shan District, Taoyuan City 333, Taiwan

ProbeLeader Co. Ltd., Hsinchu City 300, Taiwan

Field Application Engineering Department, Innolux Corp., Miola County 350, Taiwan

Received 9 February 2015; Accepted 4 May 2015

Academic Editor: Rui Wang

Copyright © 2015 Chih-Yao Huang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Butting-inserted pickup layout style could result in severe ESD degradation of NMOS devices beyond deep submicron technology. A split island layout style of butting-inserted substrate pickups is designed for a multifinger NMOS structure to enhance its ESD reliability. This layout style divides the substrate pickup diffusion bands along the whole polygate finger direction into segmented diffusion islands in the source area. This layout technique could improve the TLP second breakdown current of the 1.8 V butting pickup structure by 58~66% and 1.8 V-3.3 V inserted pickup case by 2.8 times. This style also shows excellent enhancement for the ESD-HBM levels of the 1.8 V and 3.3 V butting pickup case by 2.1~2.3 times and 18%~6 times, respectively, and the 1.8 V and 3.3 V inserted pickup case by 2.4~2.9 times and 13%~6 times, respectively. This simple technique could restore the ESD threshold level of the butting-inserted pickup layout style back to that of the normal GGNMOS without any further area consumption or fabrication cost.





Author: Chih-Yao Huang, Fu-Chien Chiu, Bo-Chen Lin, and Po-Kung Song

Source: https://www.hindawi.com/



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