Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded CoresReport as inadecuate




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VLSI Design - Volume 14 2002, Issue 3, Pages 273-286

VLSI Design Laboratory, Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece

Received 21 August 2000; Revised 18 January 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A systematic methodology for energy dissipation reduction of multimedia applications realized on architectures based on embedded cores and application specific data memory organization is proposed. Performance and area are explicitly taken into account. The proposed methodology includes two major steps: A high-level code transformation step that reorganizes the original description of the target application. The second major step includes the determination of the processor, memory and bus organization of the system and is briefly described. Experimental results from several real-life demonstrators prove the impact of the high level step of the proposed methodology.





Author: N. D. Zervas, K. Masselos, Y. A. Karayiannis, and C. E. Goutis

Source: https://www.hindawi.com/



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