A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault ConditionsReport as inadecuate




A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault Conditions - Download this document for free, or read online. Document in PDF available to download.

Active and Passive Electronic Components - Volume 2016 2016, Article ID 9414901, 12 pages -

Research ArticleDepartment of Mechatronics, Center of Energy Technology ZET, University of Bayreuth, Universitätsstraße 30, 95447 Bayreuth, Germany

Received 1 June 2016; Revised 13 July 2016; Accepted 1 August 2016

Academic Editor: Jinlong Liu

Copyright © 2016 Andreas Maerz et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application.





Author: Andreas Maerz, Teresa Bertelshofer, and Mark-M. Bakran

Source: https://www.hindawi.com/



DOWNLOAD PDF




Related documents