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(2010)Handbook of signal processing systems.p.449-484 Mark abstract Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-1153474



Author: Bjorn De Sutter , Praveen Raghavan and Andy Lambrechts

Source: https://biblio.ugent.be/publication/1153474



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