Guaranteed passive parameterized model order reduction of the partial element equivalent circuit PEEC methodReport as inadecuate




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(2010)IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY.52(4).p.974-984 Mark abstract The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach.

Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-1163358



Author: Francesco Ferranti, Giulio Antonini, Tom Dhaene and Luc Knockaert

Source: https://biblio.ugent.be/publication/1163358



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